The Open Systems Interconnection (OSI) model is a conceptual framework that characterizes and standardizes the communication functions of a telecommunications or computing system without regard to its underlying internal structure and technology. The model partitions a communication system into abstraction layers.
The physical layer (PHY) is responsible for transmission and reception of unstructured raw data between a device and a physical transmission medium. Layer specifications define characteristics such as voltage levels, timing of voltage changes, physical data rates, maximum transmission distances, and physical connectors. This includes the layout of pins, voltages, line impedance, cable specifications, signal timing and frequency for wireless devices. The components of a physical layer can be described in terms of a network topology. An example of a protocol using the physical layer is Ethernet (as defined by the Institute of Electrical Electronics Engineers (IEEE) 802.3 standard described at standards.ieee.org).
The data link layer provides node to node data transfer—a link between two directly connected nodes. It defines the protocol to establish and terminate a connection between two physically connected devices. It also defines the protocol for flow control between them. In one example, the IEEE 802.3 Ethernet standard divides the data link layer into two sublayers: a) medium access control (MAC) layer—responsible for controlling how devices in a network gain access to a medium and permission to transmit data; and b) logical link control (LLC) layer—responsible for identifying and encapsulating network layer protocols, and controls error checking and frame synchronization.
In some cases there are difficulties in connecting external PHY devices to a MAC device (such as an Ethernet network interface controller (NIC) for example). One approach is to integrate the PHY device into the MAC device (called an internal PHY approach). However, this approach introduces various limitations on capabilities that are delivered by the PHY modules. Significantly, the internal PHY approach provides no ability to switch to a different, more suitable PHY device (for example in terms of better supported connections, better supported temperature range, and so on).
Another approach is to use an external PHY device but with a connection over a serializer/deserializer (SERDES) interface. A SERDES interface includes a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The primary use of a SerDes is to provide data transmission over a single line or a differential pair in order to minimize the number of I/O pins and interconnects. In this approach the connection to the external PHY device is achieved with the use of an integrated circuit that is capable of converting parallel data into the data's serial equivalent and vice versa. Unfortunately, some external PHY devices do not support a SERDES connection. Thus, a better approach is needed.